iCAT Lab Research
Ongoing research
Think beyond limits. Build beyond expectations.
Hardware Acceleration for Sparse Computations
Sparsity reduces storage and arithmetic, but it also destroys the regularity that conventional vector and matrix engines rely on. We revisit sparse computation from first principles: representing irregular workloads as graphs, exposing hidden parallelism and reusable structure through graph transformation, and carrying those insights into compilers and accelerator dataflows.
Current work extends non-contiguous tiling and quantifiable reuse from sparse-dense matrix multiplication to sparse tensor contraction, sparse-sparse multiplication, graph learning, and scientific workloads. The goal is a common foundation that couples theory with efficient execution on GPUs and domain-specific hardware.
- Graph formulations that preserve and exploit unstructured sparsity
- Irregular tiling, dataflow, workload balancing, and memory-reuse optimization
- Accelerators for sparse matrices, tensors, nonlinear solvers, and graph models
- Graph-transformation theory and vertex decomposition. Enabled non-contiguous tiling and quantifiable reuse for sparse-dense matrix multiplication, increasing average data reuse from 32% to 72%.
- Co-occurrence graph representation for high-dimensional tensor contraction. Exposed reusable structure across irregular tensor operations and achieved 67% average data reuse.
Versatile and Flexible Architectures for Artificial Intelligence
Large language models are becoming multimodal systems that combine language, vision, retrieval, graph reasoning, and action. Their kernels vary in tensor layout, arithmetic precision, compute intensity, sparsity, and communication behavior, making a single rigid dataflow inefficient.
We design adaptable architectures that identify regular communication patterns across heterogeneous tensors, switch efficiently among spatial and temporal dataflows, and fuse kernels to keep intermediate data on chip. This direction also develops lower-complexity graph learning and retrieval algorithms so that broader receptive fields do not require proportionally more computation.
- Reconfigurable compute and memory systems for multimodal and generative models
- Unified dataflows across attention, graph, vision, retrieval, and action kernels
- Algorithm-hardware co-design for precision, sparsity, and receptive-field scaling
- Adapt-NoC flexible communication fabric. Developed an adaptable interconnect that supports heterogeneous dataflows and extends flexible communication across chiplet-based systems.
- Venus versatile accelerator architecture. Maximized data locality for deep-learning inference while regularizing communication patterns across diverse models and dataflows.
Intelligent Infrastructure for Chip Design
Chip design remains slow and inaccessible because architectural intent, RTL, logic synthesis, and physical design are separated by semantic gaps and costly iteration. We are building intelligent infrastructure that makes microarchitecture a first-class object throughout the design flow.
The foundation combines fast, accurate power-performance-area prediction with a source-to-source RTL compiler. A semantics-preserving intermediate representation retains essential logic information, enabling early-stage physical optimization to guide architecture exploration.
- Reproducible representations and benchmarks from architecture to RTL
- Rapid post-place-and-route PPA prediction without full implementation
- Compiler-guided timing closure and early microarchitecture design-space exploration
- Our proprietary tool predicts post-place-and-route delay directly from an early technology-mapped netlist, achieving an average 713× runtime speedup over the conventional ASIC implementation flow.
- Our proprietary tool performs architecture-aware RTL optimization on industry-scale designs, improving peak frequency by 6.6%–13.45% over a state-of-the-art commercial synthesis tool while achieving an average 100× runtime speedup.
Interested in these directions?
We're always looking for motivated Ph.D. students and collaborators interested in computer architecture, hardware accelerators, and AI-assisted chip design.
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