Publications

Publications & patents

“There is nothing so useless as doing efficiently that which should not be done at all.”

— Peter F. Drucker

DBLP profile →

2026

IEEE/ACM International Symposium on Microarchitecture (MICRO 2026) · Athens, Greece · to appear

KAIROS: Fast Microarchitectural Design Space Exploration by Bridging Architectural Semantics and Logic Gates top-tier

Shilin Tian, Sanjay Gandham, Lingxiang Yin, Mingjie Lin, Hao Zheng
IEEE/ACM International Symposium on Microarchitecture (MICRO 2026) · Athens, Greece · to appear

Argus: An Efficient Accelerator Design for Sparse Nonlinear Solver top-tier

Fangzhou Ye, Amir Ghazizadeh Ahsaei, Hao Zheng
IEEE/ACM International Symposium on Microarchitecture (MICRO 2026) · Athens, Greece · to appear

DireLeak: Cross-socket Cache Timing Channels Exploiting Memory Directory top-tier

Md Hafizul Islam Chowdhuryy, Kunbei Cai, Zhenkai Zhang, Hao Zheng, Fan Yao
IEEE/ACM International Symposium on Microarchitecture (MICRO 2026) · Athens, Greece · to appear

MOSAIC: An Accelerator Design for Heterophilic Graph Learning top-tier

Fangzhou Ye, Wei Zhang, Ahmed Louri, Hao Zheng
International Conference on Neuro-Symbolic Systems (NeuS 2026) · Los Angeles, CA

Neuro-Symbolic Safety Guidance for Vision-Language-Action Models via Constrained Flow Matching

William H. English, Hao Zheng, Rickard Ewetz
ACM/IEEE International Symposium on Computer Architecture (ISCA 2026) · Raleigh, NC

TensorPrism: Rethinking Sparse High-order Tensor Acceleration via Co-occurrence Graph top-tier

Fangzhou Ye, Shilin Tian, Amir Ghazizadeh Ahsaei, Hao Zheng

PDF
Design Automation Conference (DAC 2026) · Long Beach, CA

PanGaea: A Unified Memory-Efficient Accelerator for Pangenome Chaining and Alignment top-tier

Shilin Tian, Fangzhou Ye, Amir Ghazizadeh Ahsaei, Wei Zhang, Hao Zheng
IEEE International Symposium on High-Performance Computer Architecture (HPCA 2026) · Sydney, Australia

Scaling Graph Neural Network Training via Geometric Optimization top-tier

Fangzhou Ye, Lingxiang Yin, Hao Zheng

DOI

2025

Conference on Neural Information Processing Systems (NeurIPS 2025) · San Diego, CA

GAMMA: Gated Multi-hop Message Passing for Homophily-Agnostic Node Representation in GNNs top-tier

Amir Ghazizadeh Ahsaei, Rickard Ewetz, Hao Zheng

Code
IEEE/ACM International Symposium on Microarchitecture (MICRO 2025) · Seoul, South Korea

Rethinking Tiling and Dataflow for SpMM Acceleration: A Graph Transformation Framework top-tier

Amir Ghazizadeh Ahsaei, Lingxiang Yin, Shilin Tian, Fangzhou Ye, Fan Yao, Hao Zheng

PDF DOI
ACM/IEEE International Symposium on Computer Architecture (ISCA 2025) · Tokyo, Japan

DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference top-tier

Jiaqi Yang, Hao Zheng, Ahmed Louri

PDF DOI
IEEE International Symposium on High-Performance Computer Architecture (HPCA 2025) · Las Vegas, NV

I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators top-tier

Jiaqi Yang, Hao Zheng, Ahmed Louri

PDF DOI

2024

IEEE/ACM International Symposium on Microarchitecture (MICRO 2024) · Austin, TX

SCALE: A Structure-Centric Accelerator for Message Passing Graph Neural Networks top-tier

Lingxiang Yin, Sanjay Gandham, Mingjie Lin, Hao Zheng

PDF
IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2024) · New Jersey

CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation top-tier

Sanjay Gandham, Joe Walston, Sourav Samanta, Lingxiang Yin, Hao Zheng, Mingjie Lin, Stelios Diamantidis
ACM/IEEE International Symposium on Computer Architecture (ISCA 2024) · Buenos Aires, Argentina

MetaLeak: Uncovering Side Channels in Secure Memory Architectures Exploiting Metadata top-tier

Md Hafizul Chowdhuryy, Hao Zheng, Fan Yao
Design Automation Conference (DAC 2024) · San Francisco, CA

EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization top-tier

Fangzhou Ye, Lingxiang Yin, Amir Ghazizadeh Ahsaei, Hao Zheng
Design Automation Conference (DAC 2024) · San Francisco, CA

VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design top-tier

Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, Hao Zheng

Project Code
IEEE International Parallel and Distributed Processing Symposium (IPDPS 2024) · San Francisco, CA

Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks

Jiaqi Yang, Hao Zheng, Ahmed Louri
IEEE Trans. Parallel Distrib. Syst. (TPDS), 2024

Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration

Jiaqi Yang, Hao Zheng, Ahmed Louri

DOI
Asia and South Pacific Design Automation Conference (ASP-DAC 2024) · Tokyo, Japan

Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms

Sven Thijssen, Muhammad Rashedul Haq Rashed, Hao Zheng, Sumit Kumar Jha, Rickard Ewetz

2023

IEEE International Conference on Computer Design (ICCD 2023) · Washington, DC

Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration

Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, Hao Zheng

PDF
IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2023) · San Francisco, CA

ARIES: Accelerating Distributed Training in Chiplet-based Systems via Flexible Interconnects top-tier

Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng

PDF
IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2023) · San Francisco, CA

SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-optimal Workload Balance top-tier

Sanjay Gandham*, Lingxiang Yin*, Hao Zheng, Mingjie Lin (*co-first authors)

PDF
IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2023) · San Francisco, CA

Path-based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications top-tier

Muhammad Rashedul Haq Rashed, Sven Thijssen, Hao Zheng, Sumit Kumar Jha, Rickard Ewetz
Design Automation Conference (DAC 2023) · San Francisco, CA

Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications top-tier

Jiaqi Yang, Hao Zheng, Ahmed Louri
ACM/IEEE International Symposium on Computer Architecture (ISCA 2023) · Orlando, FL

FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations top-tier

Jiajun Li, Yuxuan Zhang, Hao Zheng, Ke Wang
ACM Great Lakes Symposium on VLSI (GLSVLSI 2023)

Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework

Lingxiang Yin, Jun Wang, Hao Zheng
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2023) · Marina Del Rey, CA

Poster: OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference

Sanjay Gandham, Lingxiang Yin, Hao Zheng, Mingjie Lin
IEEE Trans. Sustain. Comput. (TSUSC), 2023

Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration

Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri

DOI
J. Comput. Sci. Technol. (JCST), Feb. 2023

GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators

Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri

2022

IEEE Trans. Circuits Syst. I (TCAS-I), Apr. 2022

ASCEND: A Scalable and Energy-Efficient DNN Accelerator with Photonic Interconnects

Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth
ACM Great Lakes Symposium on VLSI (GLSVLSI 2022)

Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation

Jiaqi Yang, Hao Zheng, Ahmed Louri
Design, Automation and Test in Europe Conference (DATE 2022)

AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems

Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri

2021

IEEE Trans. Parallel Distrib. Syst. (TPDS), 2021

SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator with Workload Balancing

Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri
IEEE Trans. Sustain. Comput. (TSUSC), 2021

SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design

Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri
IEEE International Symposium on High-Performance Computer Architecture (HPCA 2021) · Seoul, South Korea

Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architecture top-tier

Hao Zheng, Ke Wang, Ahmed Louri

Patents

U.S. Patent US 11502934 B2 · Granted Nov. 2022

EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs

Hao Zheng, Ahmed Louri
U.S. Patent US 11489788 B2 · Granted Nov. 2022

A Versatile and Flexible Interconnection Network Design for Chiplet-Based Manycore Architecture

Hao Zheng, Ke Wang, Ahmed Louri
U.S. Patent 63/019,720 · Granted Jan. 2025

Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework

Ke Wang, Hao Zheng, Ahmed Louri
U.S. Patent 63/665,776 · Filed Jul. 2024 · Pending

Versatile Accelerator Design for Multiple Deep Neural Network Applications

Jiaqi Yang, Hao Zheng, Ahmed Louri

"Top-tier" conferences are those listed by csrankings.org.